1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a high voltage generating circuit for a semiconductor memory device, which generates a constant high voltage relatively higher than an external power source voltage VDD.
2. Discussion of the Related Art
A background art high voltage generating circuit for a semiconductor memory device will be described with reference to the accompanying drawings.
In the background art high voltage generating circuit for a semiconductor memory device, a flash memory is used as the semiconductor memory device.
FIG. 1 is a block diagram illustrating a background art high voltage generating circuit for a semiconductor memory device.
As shown in FIG. 1, the background art high voltage generating circuit for a semiconductor memory device includes a first clock generator 5, a second clock generator 6, a first pump 7, a second pump 8, an external voltage adjustment portion 9, an erase pump 11, and a wordline boost portion 10.
The first clock generator 5 outputs a first clock signal CLK1 by inputting an internal oscillator signal OSC and an enable signal SVPP enabled during program and erasure mode. The operation of the first clock generator 5 is controlled by a first control signal STOP1 from the external voltage adjustment portion 9.
The second clock generator 6 outputs a second clock signal CLK2 by inputting the external oscillator signal OSC and the enable signal SVPP enabled during program and erasure mode. The operation of the second clock generator 6 is controlled by a second control signal STOP2 from the external voltage adjustment portion 9.
The first pump 7 outputs a first pumping voltage VHI of high level by inputting the first clock signal CLK1. The second pump 8 outputs a second pumping voltage VVHI higher than the first pumping voltage VHI by inputting the second clock signal CLK2 and the first pumping voltage VHI.
The external voltage adjustment portion 9 receives the first and second pumping voltages VHI and VVHI, the enable signal SVPP and a reference voltage VREF, and outputs the first and second control signals STOP1 and STOP2 for controlling the first and second clock generators 5 and 6. The external voltage adjustment portion 9 outputs external control voltages VPGG, VPG and VPP to a row decoder 2, a column decoder 3, and a Y-access portion 4, respectively.
The wordline boost portion 10 boosts voltage of a wordline during read mode so as to output it to the row decoder 2.
The erase pump 11 outputs an erase voltage by inputting the first and second pumping voltages VHI and VVHI.
Each block of the aforementioned background art high voltage generating circuit for a semiconductor memory device will be described below.
As shown in FIG. 2, the wordline boost portion 10 includes a first NMOS transistor NM1 whose drain electrode is connected to a power source voltage VDD terminal, for being operated by inputting a precharge bar signal PRECH to a gate electrode, first and second inverters 14 and 15 connected between a clock signal KICK input terminal and a source electrode of the first NMOS transistor NM1, for inverting the clock signal KICK, a first capacitor C1 formed between the first inverter and the source electrode of the first NMOS transistor NM1, a second capacitor C2 formed between the second inverter and the source electrode of the first NMOS transistor NM1, a control logic 13 for outputting an enable signal for enabling the first and second inverters 14 and 15, and a voltage detecting circuit 12 for outputting a voltage which operates the control logic 13. The boosted wordline voltage VPGG is output through a junction node N1 between the first NMOS transistor NM1 and the first and second capacitors C1 and C2.
The first pump 7 includes a plurality of pumping operation portions (first, second, third, fourth and fifth pumping operation portions) for pumping the power source voltage to high voltage by inputting the first clock signal CLK1 of the first clock generator 5, and a control signal generator for generating first and second switching voltages TCKX and TCKY for transferring the pumped voltage of each pumping operation portion to the next node.
The first pumping operation portion of the first pump, which outputs the first and second pumping voltages, will be described with reference to FIG. 3a.
As shown in FIG. 3a, the first pumping operation portion includes second, third, fourth and fifth NMOS transistors NM2, NM3, NM4 and NM5 whose one electrodes are commonly connected to the power source voltage VDD terminal, a first MOS capacitor MC1 connected between the other electrode of the second NMOS transistor NM2 and a first delay portion for delaying the first clock signal CLK1, a seventh NMOS transistor NM7 connected between the other electrode of the second NMOS transistor NM2 and a second contact node CN2, a sixth NMOS transistor NM6 connected between the other electrode of the second NMOS transistor NM2 and a gate electrode of the seventh NMOS transistor NM7, whose gate electrode is connected to a gate electrode of the third NMOS transistor NM3 and the other electrode of the fourth NMOS transistor NM4, a first switching voltage TCKX input terminal for controlling the seventh NMOS transistor NM7, a second MOS capacitor MC2 formed between the first switching voltage TCKX input terminal and the gate electrode of the seventh NMOS transistor NM7, a third MOS capacitor MC3 between the other electrode of the fifth NMOS transistor NM5 and a second delay portion for delaying an inverted signal CLK1Y of CLK1, a ninth NMOS transistor NM9 connected between the other electrode of the fifth NMOS transistor NM5 and a third contact node CN3, an eighth NMOS transistor NM8 formed between the other electrode of the fifth NMOS transistor NM5 and a gate electrode of the ninth NMOS transistor NM9, whose gate electrode is connected to the gate electrode of the fourth NMOS transistor NM4 and the other electrode of the third NMOS transistor NM3, a second switching voltage TCKY input terminal for controlling the ninth NMOS transistor NM9, and a fourth MOS capacitor MC4 formed between the second switching voltage TCKY input terminal and the gate electrode of the ninth NMOS transistor NM9.
The second pumping operation portion for pumping the first and second pumping voltages to third and fourth pumping voltages includes a fifth MOS capacitor MC5 connected between the second contact node CN2 and a third delay portion for delaying the CLK1Y signal, an eleventh NMOS transistor NM11 formed between the second contact node CN2 and a fourth contact node CN4, a tenth NMOS transistor NM10 formed between the second contact node CN2 and a gate electrode of the eleventh NMOS transistor NM11, a second switching voltage TCKY input terminal of the first pump for inputting a control signal of the eleventh NMOS transistor NM11, a seventh MOS capacitor MC7 connected between the gate electrode of the eleventh NMOS transistor NM11 and the second switching voltage TCKY input terminal, a sixth MOS capacitor MC6 connected between the third contact node CN3 and a fourth delay portion for delaying the first clock signal CLK1, a thirteenth NMOS transistor NM13 formed between the third contact node CN3 and a fifth contact node CN5, a twelfth NMOS transistor NM12 formed between the third contact node CN3 and the gate electrode of the thirteenth NMOS transistor NM13, a first switching voltage TCKX input terminal of the first pump for controlling the thirteenth NMOS transistor NM13, and an eighth MOS capacitor MC8 connected between the gate electrode of the thirteenth NMOS transistor NM13 and the first switching voltage TCKX input terminal. The gate electrode of the tenth NMOS transistor NM10 is connected to the third contact node CN3 and the gate electrode of the twelfth NMOS transistor NM12 is connected to the second contact node CN2.
The third pumping operation portion has the same construction as the second pumping operation portion except that CLK1Y and CLK1 are changed to each other, and the first switching voltage TCKX of the first pump and the second switching voltage TCKY of the first pump are changed to each other.
The fourth pumping operation portion has the same construction as the second pumping operation portion.
The fifth pumping operation portion has the same construction as the third pumping operation portion.
The control signal generator for outputting the first switching voltage TCKX of the first pump and the second switching voltage TCKY of the first pump will be described with reference to FIG. 3b.
As shown in FIG. 3b, the control signal generator includes fourteenth, fifteenth, sixteenth and seventeenth NMOS transistors NM14, NM15, NM16 and NM17 whose one electrodes are commonly connected to the power source voltage VDD terminal, a ninth MOS capacitor MC9 connected between the other electrode of the fourteenth NMOS transistor NM14 and an eleventh delay portion for delaying the first clock signal CLK1, a first PMOS pass transistor whose one electrode is connected to the other electrode of the fourteenth NMOS transistor NM14, for passing the first switching voltage TCKX, an eighteenth NMOS transistor NM18 connected between the other electrode of the first PMOS pass transistor and the ground voltage VSS terminal, for being operated by a signal of a thirteenth delay portion for delaying the CLK1Y signal, a tenth MOS capacitor MC10 connected between the other electrode of the seventeenth NMOS transistor NM17 and a twelfth delay portion for delaying the CLK1Y signal, a second PMOS pass transistor whose one electrode is connected to the other electrode of the seventeenth NMOS transistor NM17, for passing the second switching voltage TCKY of the first pump, and a ninth NMOS transistor NM19 connected between the other electrode of the second PMOS pass transistor and the ground voltage VSS terminal, for being operated by a signal of a fourteenth delay portion for delaying the CLK1 signal. The gate electrode of the fifteenth NMOS transistor NM15 is connected to the other electrodes of the sixteenth and seventeenth NMOS transistors NM16 and NM17, and the gate electrode of the sixteenth NMOS transistor NM16 is connected to the other electrodes of the fourteenth and fifteenth NMOS transistors NM14 and NM15. One electrodes of the fourteenth and seventeenth NMOS transistors NM14 and NM17 are connected to each gate electrode thereof. The power source voltage VDD is applied to the gate electrodes of the first and second PMOS pass transistors.
The operation of the aforementioned background art high voltage generating circuit for a semiconductor memory device will be described below.
As shown in FIG. 1, during program and erasure mode, the first and second clock generators 5 and 6 generate the first and second clock signals CLK1 and CLK2 by inputting the program and erasure enable signal SVPP, the internal OSC signal, and the control signals STOP1 and STOP2 of the external voltage adjustment portion 9. The first pump 7 to which the first clock signal is input outputs high voltage of VHI for program and erasure by pumping operation as shown in FIGS. 3a and 3b. At this time, VHI voltage is pumped to a high voltage of 6 VDD by the first pump 7. Likewise, the second pump 8 to which the second clock signal is input outputs high voltage VVHI by repeated pumping operation. Thereafter, the external voltage adjustment portion 9 which receives the pumped voltages VHI and VVHI outputs VPGG to the row decoder 2 for outputting the wordline control signal to the semiconductor memory cell, and supplies VPG and VPP to the column decoder 3 and the Y-access portion 4, respectively, for outputting drain control signals of the semiconductor memory cell.
At this time, if VHI and VVHI are higher than a target voltage, the external voltage adjustment portion 9 enables the control signals STOP1 and STOP2 to disable the first and second clock signals, so that the pumping operation is stopped. If VHI and VVHI are lower than the target voltage, the external voltage adjustment portion 9 disables the control signals STOP1 and STOP2 to enable the first and second clock signals, so that the pumping operation continues. Such a high voltage is applied to the semiconductor memory device so that program and erasure operation can be performed.
At read and standby mode, VPGG, VPG, and VPP voltage are output to the semiconductor memory device by the aforementioned operation. If the memory cell is erased, threshold voltage of the memory cell has an almost constant value regardless of the external voltage such as VDD. At this time, if the external voltage VDD becomes low, threshold voltage of the erased cell has a value relatively higher than VDD. Thus, current value of the erased cell is greatly varied. Finally, speed for reading the cell becomes slow.
In reading operation, if the wordline control voltage VPGG of the semiconductor memory cell is output by the wordline boost portion 10, as shown in FIG. 2, the wordline voltage level is adjusted by the VDD voltage detecting circuit 12, the control logic 13, the first and second inverters, and the first and second capacitors. At this time, if the precharge bar signal becomes high to turn on the first NMOS transistor, the wordline control voltage VPGG is boosted to the junction node N1. At this time, the wordline control voltage depending on the external power source voltage VDD is greatly varied and the external power source voltage is sensitive to noise, thereby causing error of the chip. Also, when the external power source voltage VDD level has the maximum value, the wordline control voltage VPGG becomes high.
The aforementioned background art high voltage generating circuit for a semiconductor memory device has several problems.
First, in case of reading operation at low power source voltage, threshold voltage of the erased cell is distributed relatively higher than the power source voltage, thereby causing slow reading operation speed. In addition, since the wordline control voltage level is greatly varied when the power source voltage has the maximum value, program is disturbed during reading operation, thereby deteriorating reliability of the operation.